library verilog;
use verilog.vl_types.all;
entity compare_4 is
    port(
        x               : in     vl_logic_vector(3 downto 0);
        y               : in     vl_logic_vector(3 downto 0);
        data_out        : out    vl_logic_vector(2 downto 0);
        enable          : in     vl_logic
    );
end compare_4;
